[NCLUG] July 1, 2003 talk - Linux System Performance
Matt Taggart
matt at lackof.org
Sat Jun 28 11:57:02 MDT 2003
jbass at dmsd.com writes...
> What a cool chip ... looks like about 128KB integrated
> L1 cache for really great performance. Did you compile
> with -O, or is the TLB misses on this beastie just really
> poor?
It was unoptimized like your original example, -O and -O2 results below.
More info about the processor at,
http://www.via.com.tw/en/Products/eden.jsp
There are whitepapers and stuff at the bottom. One of them says,
* Two 64-KB primary (L1) caches with 4-way associativity
* A 4-way 64-KB unified level-2 (L2) cache
* Two 128-entry TLBs with 8-way associativity
Matt
-----------------------------------------------------------------------
taggart at gateway:~$ ./mbenchO
Mbench by John. L. Bass, DMS Design copyright 1985-1996
You are free to copy and use this program providing configuration info
and results are shared with the author by email to jbass at dmsd.com
Counts are per clock tick, presumed to be HZ=100
SetSize Random Sequential
-------- ------------- ------------- 0% 25% 50% 75% 100%
1024 674457 100% 1635009 100% | | * | | @
1536 674464 100% 1636645 100% | * @
2048 675139 100% 1635005 99% | | * | | @
3072 675136 100% 1635008 99% | * @
4096 675136 100% 1635008 99% | | * | | @
6144 674462 100% 1635008 99% | * @
8192 674464 100% 1635008 99% | | * | | @
12288 675139 100% 1635008 99% | * @
16384 674462 100% 1635008 99% | | * | | @
24576 675139 100% 1635008 99% | * @
32768 675136 100% 1635008 99% | | * | | @
49152 674462 100% 1633375 99% | * @
65536 672447 99% 1623634 99% | | * | | @
98304 558997 82% 183456 11% | @ *
131072 439136 65% 132326 8% | @ |* | | |
196608 226238 33% 60412 3% | @ *
262144 149728 22% 60416 3% | @ * | | | |
393216 101467 15% 60356 3% | @*
524288 82515 12% 60352 3% | @ | | | |
786432 61408 9% 60112 3% | @
1048576 54400 8% 60156 3% |*@ | | | |
1572864 48975 7% 60220 3% |*@
2097152 46464 6% 60164 3% |*@ | | | |
3145728 44096 6% 60100 3% |*@
4194304 42937 6% 60156 3% |*@ | | | |
6291456 41653 6% 60220 3% |*@
8388608 40927 6% 60164 3% |*@ | | | |
12582912 39775 5% 60160 3% |*@
16777216 38617 5% 60220 3% |*@ | | | |
-----------------------------------------------------------------------
taggart at gateway:~$ ./mbenchO2
Mbench by John. L. Bass, DMS Design copyright 1985-1996
You are free to copy and use this program providing configuration info
and results are shared with the author by email to jbass at dmsd.com
Counts are per clock tick, presumed to be HZ=100
SetSize Random Sequential
-------- ------------- ------------- 0% 25% 50% 75% 100%
1024 674603 100% 1684080 100% | | * | | @
1536 675267 100% 1682414 99% | * @
2048 675264 100% 1684084 100% | | * | | @
3072 675264 100% 1684096 100% | * @
4096 674589 99% 1684096 100% | | * | | @
6144 674592 99% 1684096 100% | * @
8192 674592 99% 1684096 100% | | * | | @
12288 674592 99% 1684096 100% | * @
16384 675267 100% 1682414 99% | | * | | @
24576 674589 99% 1684084 100% | * @
32768 674592 99% 1684096 100% | | * | | @
49152 674592 99% 1682414 99% | * @
65536 673246 99% 1677368 99% | | * | | @
98304 558240 82% 182294 10% | @ *
131072 390368 57% 100036 5% | @ *| | | |
196608 208864 30% 63040 3% | @ *
262144 141838 21% 60732 3% | @ * | | | |
393216 99697 14% 60675 3% | @*
524288 81874 12% 60611 3% | @ | | | |
786432 61280 9% 60427 3% | @
1048576 54368 8% 60476 3% |*@ | | | |
1572864 49041 7% 60420 3% |*@
2097152 46414 6% 60416 3% |*@ | | | |
3145728 44096 6% 60476 3% |*@
4194304 42979 6% 60420 3% |*@ | | | |
6291456 41204 6% 60476 3% |*@
8388608 40093 5% 60420 3% |*@ | | | |
12582912 38928 5% 60476 3% |*@
16777216 37957 5% 60480 3% |*@ | | | |
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