[NCLUG] Re: parallel processing users?

[Matt]

John wrote:

 > Actually, it's quite rational to do so, but it takes developing a compiler
 > that will reduce C/Fortan into several different types of netlists to fit
 > the problems into FPGA's. Key is that it does take a pretty stiff relearning
 > the basic principles of architecture and machine design, as what "everybody
 > knows" is the right or only way to build machines, quickly leads you down
 > the wrong path for this class of machines.

My brief experience with using FPGAs and C is that C doesn't seem like
the right tool.  In order to get anything to work well I had to think
in terms of data flow and placing/connecting functional units.  That's
not C.  But verilog is too low a level if you're talking about 1000s
of lines of code and scientists that are more interested in science
than circuit design.

 > I actually proposed doing so as a $30-50M project to Sandia earlier this year
 > with the intent to produce a 1-10 petaflop FPGA/Memory machine specifically
 > targeting their large simulation applications. Both the nature of the compiler,
 > and the architecture of the machine, are critical aspects to realizing usable
 > solutions, along with a critically strong dose of keep it simple.

Well, I suppose if you made a big homogenous sea of
memory/FPGA/floating point units it could be much simpler to figure
out and work with than the complexity of a typical cpu.

 > Language/tool support, cosmic radiation, and "nobody has done it before" are
 > the three primary problems. The first and last are really the primary problems,

Language and tool support seems to be a big problem with all
performance related software.  C and the like are too generic and far
away from the problem and require super human optimizers or low level
mucking around by the programmer.  My approach is to work on specific
extensions for specific problems.  I say this because I build my own
tools and that's what works for me.  If you have a specific
application from Sandia and specific hardware, you're half way there.

 > So in the mean time, I'm still investing my own money into a several thousand
 > FPGA proof-of-concept prototype built out of Xilinx Virtex, Virtex-2, and
 > Virtex-Pro parts. It's taken that last year being patient on ebay to find

I'd like to see that.

 > most of the rest of the parts, but I'm very close to bringing the entire BOM
 > in-house so I can finally actually fab such a machine as "my home super computer".
 > it's been fun, but what else does and oldie moldie UNIX guy do these days :)

uh

 > 
 > Next project will be to bring a team togather that can self fund the remainder
 > of the development without a formal Angel/VC seed, and form the core for a next
 > generation team to build reconfigurable supercomputers, and bypass the VC market.
 > The market is getting close to ripe for this technology, and I'm reaching the
 > limits of what can do as a one man project (actually I've been way over my head
 > for several years, but that has been the fun part of this learning/development
 > curve).
 > 
 > John